1. Field of the Invention
The present invention generally relates to caching architectures and, more specifically, to a system and method for explicitly managing cache coherence.
2. Description of the Related Art
Most modern microprocessors include some form of instruction and data caching, where a small but fast cache memory speeds up access to a main memory. At the simplest level, a cache memory can pre-load blocks of memory from main memory so that the processor need not stall when performing a load. This is possible because (a) a processor usually accesses sequential memory locations and (b) loading more than one sequential memory location at the same time is faster than loading each sequential memory location one by one.
In a multi-processor environment, two or more processors may share access to the same area of main memory via corresponding cache memories. Such sharing could lead to cache corruption. For example, processor P may store cache lines of data associated with the particular area in a corresponding cache memory, including any changes that may have been made to the data. Processor Q may then load a cache line associated with the particular area from the main memory. Because the first processor stores a (possibly modified) copy of the data in the corresponding cache memory, the data loaded by the second processor may not be the most current data. Such a scenario may lead to cache corruption.
To avoid cache corruption in a multi-processor environment, a cache coherence protocol is often implemented to provide a coherent shared memory for multiple processors. As a result of a cache coherence protocol, at any point in time, processor P reading memory location A sees the most recently completed write to location A made by any other processor. To implement such cache coherence, if P makes a copy of A in its local cache memory, then the copy must be updated or invalidated when another processor Q writes location A. The implementation of cache coherence protocols comes at considerable cost. Simple read and write operations can spawn three or more messages to update directory state, invalidate stale copies, and provide acknowledgements. The transmission and tracking of such messages is not only cumbersome but also negatively impacts the performance of the system.
Accordingly, what is needed in the art is a system and method for implementing cache coherency without imposing a large messaging overhead on the system.